The present invention generally relates to a multilayer capacitor and, more particularly, to a multilayer capacitor of a type comprising a plurality of capacitors formed in a single integer.
In general, where a multilayer capacitor is to be manufactured, internal electrode layers, forming respective parts of the capacitors, and connecting conductor layers extending outwardly therefrom to the periphery of the assembly are formed so as to have a suitable surface area corresponding to a desired capacitance without being formed entirely on the same layer. Accordingly, when it comes to a currently widely employed printing method wherein desired electrode layers are formed by printing on a dielectric layer and another dielectric layer overlaying the printed electrode layers is also formed by printing, the thickness of that portion tends to increase with increase of the number of the layers even though each electrode layer is in the form of a thin film having a small thickness.
FIG. 1 of the accompanying drawings illustrates the prior art multilayer capacitor in sectional representation, which capacitor comprises a plurality of capacitor elements positioned one above the other, each capacitor element being comprised of a dielectric layer 1 and a pair of electrode layers 2 and 3 on respective sides of the dielectric layer 1. Usually, the electrode layers 2 and 3 have respective connecting conductor layers 4 and 5 connected thereto, or formed integrally therewith, and positioned in laterally offset or displaced relation to each other, said connecting conductor layers 4 and 5 being in turn connected to respective terminal electrodes 6 and 7 which are formed at the periphery of the assembly by depositing an electroconductive paste or by vapor deposition of metal. The electrode layers 2 and 3 have such patterns as shown in FIGS. 2(a) and 2(b), respectively, and the connecting conductor layers 4 and 5 are so positioned as to be in laterally offset or displaced relation to each other while the electrode layers 2 and 3 are in register with each other with the respective dielectric layer 1 held therebetween.
In the prior art multilayer capacitor so constructed as shown in FIGS. 1 and 2, the peripheral portion of the multilayer capacitor where the connecting conductor layers 4 and 5 are located has a thickness t.sub.1 which is smaller than the thickness t.sub.2 of the body portion of the same capacitor where the electrode layers 2 and 3 are located. The difference between the thicknesses t.sub.2 and t.sub.1 constitutes an undesirable peripheral indent of varying size which is larger at a peripheral portion of the multilayer capacitor where no connecting conductor layers are located, thereby causing the multilayer capacitor to have its opposite surfaces lacking in flatness. In addition, where the layers 2, 3, 4 and 5 are formed by the use of the screen printing technique, ink bulges tend to be formed between the layers 2 and 4 and also between the layers 3 and 5 at a location where the peripheral indent would subsequently be formed. The presence of the ink bulges results in increased surface area of the respective electrode layers 2 and 3 over a desired or required value, which in turn results in the increased capacitance of the multilayer capacitor over a desired or required value, thereby causing the multilayer capacitors to deviate in capacitance from one capacitor to another during the manufacture thereof.
FIG. 3 of the accompanying drawings illustrates in sectional representation another prior art multilayer capacitor of a type employing a plurality of, for example, two, sets 8 and 9 of electrode layers forming respective layered capacitor units A and B, said electrode layer sets 8 and 9 being insulated from each other. In this type of the multilayer capacitor shown in FIG. 3, the use of the screen printing technique to form the electrode layers of these sets 8 and 9 tends to result in the formation of a varying space between the laterally neighbouring pairs of the electrode layers of these two sets 8 and 9 because of the formation of ink bulges. By way of example, as shown in FIG. 3, while the lowermost electrodes of the respective sets 8 and 9 are spaced a design distance D from each other, the presence of the ink bulges tends to cause the uppermost electrode layers of the sets 8 and 9 to be spaced from each other a distance d which is smaller than the distance D. This is problematic in that, not only does the multilayer capacitor fail to have its opposite surfaces being flat, but also the voltage breakdown characteristic of the multilayer capacitor tends to be adversely affected.
According to the prior art method for making multilayer capacitors, it is a general practice to form the electrode layers simultaneously on a plurality of capacitor regions and then to separate these capacitor regions to provide respective multilayer capacitor chips. An example of this prior art method is illustrated in FIGS. 4 to 6. Referring to FIGS. 4 to 6, particularly to FIGS. 6(a) and 6(b), the multilayer capacitor is formed by repeatedly performing a required number of times a process which substantially comprises the step of forming on one surface of a dielectric layer 25 both of an electrode layer 21, including a plurality of, for example, four, electrode portions 21a, 21b, 21c and 21d occupying respective four corner areas I, II, III and IV of the dielectric layer 25, and an electrode layer 22 including a corresponding number of electrode portions 22a, 22b, 22c and 22d arranged in predetermined patterned relation to the electrode portions 21a, 21b, 21c and 21d as shown in FIG. 6(a), the step of subsequently forming an overlaying dielectric layer 26 overlaying the dielectric layer 25 with the electrode layers 21 and 22 sandwiched therebetween as shown in FIG. 6(b), and the step of forming, on one surface of the overlaying dielectric layer 26 remote from the dielectric layer 25, a counter-electrode layer 23 including a corresponding number of counter-electrode portions 23a, 23b, 23c and 23d each formed so as to overhang the associated electrode portions 21a and 22a, 21b and 22b, 21c and 22c, or 21d and 22d of the respective electrode layers 21 and 22 as shown in FIG. 6(b). The capacitor assembly so formed by repeatedly performing the above described process is, after having been dried, cut into two capacitor components along the broken line A-B as shown in FIG. 4(a) to separate the electrode portions 21a and 21c from the associated electrode portions 21b and 21d, followed by a trimming process to cut the components along the respective broken lines C-D, C'-D', E-F and G-H to provide the four multilayer capacitor chips. During the trimming process, care is required to allow connecting conductor layers 27 extending outwards from the electrode portions 22a to 22d and 23a to 23d to be exposed to the outside when the capacitor components have been so cut. Each of the capacitor chips is thereafter made up by applying or depositing an electroconductive paste to side faces of the respective chip to form electrode terminals for external electrical connection, each of said terminals connecting the exposed ends of the connecting conductor layers together so that the respective capacitor chip can have an electric equivalent circuit shown in FIG. 4(b) and having three terminals 29a, 29b and 29c. It is to be noted that the other side faces 30 of each of the capacitor chips where no connecting conductor layer is exposed are also applied with an electroconductive paste 28 to provide relay terminals through which other electric component parts can be interconnected as shown in FIG. 5. In FIG. 5, reference numeral 31 represents points of connection of the connecting conductor layers to the electrode terminals. It is also to be noted that the formation of the electrode layers 21, 22 and 23 and also that of the overlaying dielectric layers 26 are carried out by the use of the printing technique and that the number of repetition of the above described process depends on the number of the layers desired or required in the resultant multilayer capacitor.
In the above discussed art method, where the patterns of the electrode layers 21, 22 and 23 in the corner areas I and III are reversed in position with those in the corner areas II and IV, respectively, the result would be such that, since the individual blocks do not assume the identical shape, the applied voltage may differ from one block to another, tending to provide the multilayer capacitors of varying capacitance. However, where they are arranged in the manner as shown in FIG. 4, any possible deviation in capacitances among the resultant multilayer capacitors can advantageously be minimized since each block receives the same process steps, but a disadvantage is involved in that a relatively large amount of the material such as respresented by the rectangular area C-D-D'-C' in FIG. 4(a) must be disposed of. The number of the rectangular areas of the material to be disposed of increases where more than four multilayer capacitor chips are to be manufactured from a single assembly, thereby posing the increased loss of expensive material.